Instruction set simulators (ISSs) play a critical role in the design cycle of embedded systems. However, as ISSs evolve and increase in complexity, not only new bugs might be introduced but also old latent bugs might be revealed. Finding these bugs based on the simulator output might be a challenging task. This letter presents HybridVerifier, a novel and retargetable framework for ISS verification. It relies on hybrid simulation between the ISS and the host processor (x86), using the host’s memory as a reference for the simulated architecture. We demonstrate the effectiveness of our approach in three different scenarios: 1) ISS model verification; 2) processor specific libraries/functionalities; and 3) cross compiler bugs.